publication order number: mmft3055e/d ? semiconductor components industries, llc, 2006 august, 2006 ? rev. 5 1 mmft3055e power mosfet 1.7 amp, 60 volts n ? channel tmos e ? fet sot ? 223 this advanced e ? fet is a tmos medium power mosfet designed to withstand high energy in the avalanche and commutation modes. this new energy efficient device also offers a drain ? to ? source diode with a fast recovery time. designed for low voltage, high speed switching applicat ions in power supplies, dc ? dc converters and pwm motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. the device is housed in the sot ? 223 package which is designed for medium power surface mount applications. features ? silicon gate for fast switching speeds ? low r ds(on) ? 0.15 max ? the sot ? 223 package can be soldered using wave or reflow. the formed leads absorb thermal stress during soldering, eliminating the possibility of damage to the die ? available in 12 mm tape and reel use MMFT3055ET1 to order the 7 inch/1000 unit reel. use mmft3055et3 to order the 13 inch/4000 unit reel. maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drain ? to ? source voltage v dss 60 vdc gate ? to ? source voltage ? continuous v gs 20 vdc drain current ? continuous drain current ? single pulse (t p 10 s) i d i dm 1.7 6.8 adc apk total power dissipation @ t a = 25 c derate above 25 c (note 1) p d 0.8 6.3 watts mw/ c operating and storage temperature range t j , t stg ? 65 to 150 c single pulse drain ? to ? source avalanche energy ? starting t j = 25 c (v dd = 60 vdc, v gs = 10 vdc, peak i l = 1.7 apk, l = 0.2 mh, r g = 25 ) e as 168 mj thermal resistance ? junction to ambient (surface mounted) r ja 156 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 1. power rating when mounted on fr ? 4 glass epoxy printed circuit board using recommended footprint. 1 2 3 4 n ? channel device package shipping ? ordering information MMFT3055ET1 sot ? 223 1000 tape & reel sot ? 223 case 318e style 3 lww marking diagram 3055 l = location code ww = work week pin assignment 3 2 1 4 gate drain source drain mmft3055et3 sot ? 223 4000 tape & reel d s g 2,4 3 1 http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. v dss r ds(on) typ i d max 60 v 150 m 1.7 a
mmft3055e http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain ? to ? source breakdown voltage, (v gs = 0, i d = 250 a) v (br)dss 60 vdc zero gate voltage drain current, (v ds = 60 v, v gs = 0 v) i dss 10 adc gate ? body leakage current, (v gs = 20 v, v ds = 0 v) i gss 100 nadc on characteristics (note 2) gate threshold voltage, (v ds = v gs , i d = 1.0 ma) v gs(th) 2.0 4.5 vdc static drain ? to ? source on ? resistance, (v gs = 10 v, i d = 0.85 a) r ds(on) 0.15 drain ? to ? source on ? voltage, (v gs = 10 v, i d = 1.7 a) v ds(on) 0.34 vdc forward transconductance, (v ds = 15 v, i d = 0.85 a) g fs 2.2 mhos dynamic characteristics input capacitance (v ds = 20 v, v gs = 0 v, f = 1.0 mhz) c iss 430 pf output capacitance c oss 225 reverse transfer capacitance c rss 40 switching characteristics turn ? on delay time (v dd = 25 v, i d = 0.85 a v gs = 10 v, r g = 50 , r gs = 25 ) t d(on) 15 ns rise time t r 22 turn ? off delay time t d(off) 31 fall time t f 49 total gate charge (v ds = 48 v, i d = 1.7 a, v gs = 10 vdc) see figures 15 and 16 q g 12.5 nc gate ? source charge q gs 2.0 gate ? drain charge q gd 4.5 source drain diode characteristics (1) forward on ? voltage i s = 1.7 a, v gs = 0 v v sd 0.8 vdc forward turn ? on time i s = 1.7 a, v gs = 0 v, dl s /dt = 400 a/ s, v r = 30 v t on limited by stray inductance reverse recovery time t rr 50 ns 2. pulse test: pulse width 300 s, duty cycle 2%.
mmft3055e http://onsemi.com 3 r ds(on) , drain?to?source resistance (ohms) r ds(on) , drain?to?source resistance (ohms) r ds(on) , drain?to?source resistance (ohms) 10 figure 1. on region characteristics v ds , drain?to?source voltage (volts) 6 v figure 2. gate ? threshold voltage variation with temperature t j , junction temp ( c) figure 3. transfer characteristics v gs , gate?to?source voltage (volts) figure 4. on ? resistance versus drain current i d , drain current (amps) figure 5. on ? resistance versus gate ? to ? source voltage v gs , gate?to?source voltage (volts) figure 6. on ? resistance versus junction temperature t j , junction temperature ( c) v ds = v gs i d = 1 ma i d , drain current (amps) 8 6 4 2 0 10 8 6 4 2 0 v gs(th) , gate threshold voltage (normalized) 1.1 ?50 1 0.9 0.8 0.7 0 50 100 150 10 i d , drain current (amps) 8 6 2 0 10 8 6 4 2 0 0.3 0 0.2 0.15 0.1 0 24 6 8 0.25 v gs = 10 v 25 c ?55 c 0.5 0.4 0.3 0.1 0 21 15 12 9 6 3 0.3 ?50 0.1 0 0 50 100 150 0.2 0.2 18 4 0.05 5 v t j = 25 c i d = 1.7 a v gs = 10 v i d = 1.7 a v gs = 20 v 4.5 v 4 v 10 v 8 v 1.2 t j = 25 c 7 v 100 c v ds = 10 v 25 c t j = ?55 c t j = 100 c
mmft3055e http://onsemi.com 4 forward biased safe operating area the fbsoa curves define the maximum drain ? to ? source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. the curves are based on an ambient temperature of 25 c and a maximum junction temperature of 150 c. limitations for repetitive pulses at various ambient temperatures can be determined by using the thermal response curves. application note, an569, ?transient thermal resistance ? general data and its use? provides detailed instructions. switching safe operating area the switching safe operating area (soa) is the boundary that the load line may traverse without incurring damage to the mosfet. the fundamental limits are the peak current, i dm and the breakdown voltage, bv dss . the switching soa is applicable for both turn ? on and turn ? off of the devices for switching times less than one microsecond. figure 7. maximum rated forward biased safe operating area v gs = 20 v single pulse t a = 25 c dc 10 i d , drain current (amps) 0.1 1 0.1 0.01 1 10 100 v ds , drain?to?source voltage (volts) 20ms 100 ms 1 s 500ms r ds(on) limit thermal limit package limit 1.0 0.1 0.001 1.0e?05 1.0e?04 1.0e?03 1.0e?02 1.0e?01 1.0e+00 r(t), effe c tive thermal re s i s tan c e t, time (s) 0.1 0.01 0.2 0.02 0.01 d = 0.5 single pulse (normalized) 0.05 r ja (t) = r(t) r ja r ja = 156 c/w max d curves apply for power pulse train shown read time at t 1 t j(pk) ? t a = p (pk) r ja (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 1.0e+01 figure 8. thermal response commutating safe operating area (csoa) the commutating safe operating area (csoa) of figure 10 defines the limits of safe operation for commutated source ? drain current versus re ? applied drain voltage when the source ? drain diode has undergone forward bias. the curve shows the limitations of i fm and peak v ds for a given rate of change of source current. it is applicable when waveforms similar to those of figure 9 are present. full or half ? bridge pwm dc motor controllers are common applications requiring csoa data. device stresses increase with increasing rate of change of source current so di s /dt is specified with a maximum value. higher values of di s /dt require an appropriate derating of i fm , peak v ds or both. ultimately di s /dt is limited primarily by device, package, and circuit impedances. maximum device stress occurs during t rr as the diode goes from conduction to reverse blocking. v ds(pk) is the peak drain ? to ? source voltage that the device must sustain during commutation; i fm is the maximum forward source ? drain diode current just prior to the onset of commutation. v r is specified at 80% rated bv dss to ensure that the csoa stress is maximized as i s decays from i rm to zero. r gs should be minimized during commutation. t j has only a second order effect on csoa. stray inductances in on semiconductor?s test circuit are assumed to be practical minimums. dv ds /dt in excess of 10 v/ns was attained with di s /dt of 400 a/ s.
mmft3055e http://onsemi.com 5 r g t v ds l i l v dd figure 9. commutating waveforms t p bv dss v dd i l(t) t, (time) figure 10. commutating safe operating area (csoa) 15 v v gs 0 90% i fm dl s /dt i s 10% t rr t frr 0.25 i rm i rm t on v ds v f v dsl v r v ds(pk) max. csoa stress area figure 11. commutating safe operating area test circuit + ? + ? figure 12. unclamped inductive switching test circuit v r v gs i fm 20 v r gs dut i s l i v r = 80% of rated v dss v dsl = v f + l i ? dl s /dt figure 13. unclamped inductive switching waveforms v ds , drain?to?source voltage (volts) i s , source current (amps) 10 0 8 6 4 2 0 20 40 60 80 100 10 30 50 70 90 9 7 5 3 1 di s /dt 400 a/ s v ds
mmft3055e http://onsemi.com 6 figure 14. capacitance variation with voltage same devicetype as dut v in +18v v dd 10v 100k 0.1 f ferrite bead dut 100 2n3904 2n3904 47k 15v 100k v in = 15 v pk ; pulse width 100 s, duty cycle 10%. 1ma 47k figure 15. gate charge versus gate ? to ? source voltage gate?to?source or drain?to?source voltage (volts) c, capacitance (pf) c rss c iss c oss 1400 20 1200 1000 800 600 400 200 0 15 10 5 0 5 10 15 20 figure 16. gate charge test circuit q g , total gate charge (nc) 16 0 14 12 10 0 24 6 20 v gs , gate?to?source voltage (volts) v ds = 36 v 8 6 4 2 81012141618 48 v v gs v ds t j = 25 c f = 1 mhz t j = 25 c i d = 1.7 a v gs = 10 v
mmft3055e http://onsemi.com 7 package dimensions style 3: pin 1. gate 2. drain 3. source 4. drain h s f a b d g l 4 123 0.08 (0003) c m k j dim a min max min max millimeters 0.249 0.263 6.30 6.70 inches b 0.130 0.145 3.30 3.70 c 0.060 0.068 1.50 1.75 d 0.024 0.035 0.60 0.89 f 0.115 0.126 2.90 3.20 g 0.087 0.094 2.20 2.40 h 0.0008 0.0040 0.020 0.100 j 0.009 0.014 0.24 0.35 k 0.060 0.078 1.50 2.00 l 0.033 0.041 0.85 1.05 m 0 10 0 10 s 0.264 0.287 6.70 7.30 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. sot ? 223 (to ? 261) case 318e ? 04 issue k *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1.5 0.059 mm inches scale 6:1 3.8 0.15 2.0 0.079 6.3 0.248 2.3 0.091 2.3 0.091 2.0 0.079 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 mmft3055e/d e ? fet is a trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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